The present invention relates to a self-scanning light-emitting device, in particular to a cross under metal wiring structure for a self-scanning light-emitting device.
A light-emitting device in which a plurality of light-emitting elements are arrayed on the same substrate is utilized as a light source of a printer, in combination with a driver circuit. The inventor of the present invention has interest in a three-terminal light-emitting thyristor having an pnpn-structure as an element of the light-emitting device, and has already filed several patent applications (see Japanese Patent Publication Nos. 1-238962, 2-14584, 2-92650, and 2-92651.) These publications have disclosed that a self-scanning function for light-emitting elements may be implemented, and further have disclosed that such self-scanning light-emitting device has a simple and compact structure for a light source of a printer, and has smaller arraying pitch of thyristors.
The inventor has further provided a self-scanning light-emitting device having such structure that an array of light-emitting thyristors having transfer function is separated from an array of light-emitting thyristors having writable function (see Japanese Patent Publication No. 2-263668.)
Referring to FIG. 1, there is shown an equivalent circuit diagram of a fundamental structure of this self-scanning light-emitting device. According to this structure, the device comprises an array of transfer elements T1, T2, T3, . . . and an array of writable light-emitting elements L1, L2, L3, . . . , these elements consisting of three-terminal light-emitting thyristors. The structure of the portion of an array of transfer elements includes diode D1, D2, D3, . . . as means for electrically connecting the gate electrodes of the neighboring transfer elements to each other. VGK is a power supply (normally 5 volts), and is connected to all of the gate electrodes G1, G2, G3, . . . of the transfer elements via a load resistor RL, respectively. Respective gate electrodes G1, G2, G3, . . . are correspondingly connected to the gate electrodes of the writable light-emitting elements L1, L2, L3, . . . A start pulse xcfx86s is applied to the gate electrode of the transfer element T1, transfer clock pulses xcfx861 and xcfx862 are alternately applied to all of the anode electrodes of the transfer elements, and a write signal xcfx86I is applied to all of the anode electrodes of the light-emitting elements.
In FIG. 4, R1, R2 and RI designate current limiting resistors, respectively.
The operation of this self-scanning light-emitting device will now be described briefly. Assume that as the transfer clock xcfx861 is driven to a high level, the transfer element T2 is turned on. At this time, the voltage of the gate electrode G2 is dropped to a level near zero volts from 5 volts. The effect of this voltage drop is transferred to the gate electrode G3 via the diode D2 to cause the voltage of the gate electrode G3 to set about 1 volt which is a forward rise voltage (equal to the diffusion potential) of the diode D2. On the other hand, the diode D1 is reverse-biased so that the potential is not conducted to the gate G1, then the potential of the gate electrode G1, remaining at 5 volts. The turn on voltage of the light-emitting thyristor is approximated to a gate electrode potential+a diffusion potential of pn-junction (about 1 volt.) Therefore, if a high level of a next transfer clock pulse xcfx862 is set to the voltage larger than about 2 volts (which is required to turn-on the transfer element T3) and smaller than about 4 volts (which is required to turn on the transfer element T5), then only the transfer element T3 is turned on and other transfer elements remain off-state, respectively. As a result of which, on-state is transferred from T2 to T3. In this manner, on-state of transfer elements are sequentially transferred by means of two-phase clock pulses.
The start pulse xcfx86s works for starting the transfer operation described above. When the start pulse xcfx86s is driven to a low level (about 0 volt) and the transfer clock pulse xcfx862 is driven to a high level (about 2-4 volts) at the same time, the transfer element T1 is turned on. Just after that, the start pulse xcfx86s is returned to a high level. Assuming that the transfer element T2 is in the on-state, the voltage of the gate electrode G2 is lowered to almost zero volt. Consequently, if the voltage of the write signal xcfx86I is higher than the diffusion potential (about 1 volt) of the pn-junction, the light-emitting element L2 may be turned into an on-state (a light-emitting state).
On the other hand, the voltage of the gate electrode G1 is about 5 volts, and the voltage of the gate electrode G3 is about 1 volt. Consequently, the write voltage of the light-emitting element L1 is about 6 volts, and the write voltage of the light-emitting element L3 is about 2 volts. It is appreciated from this that the voltage of the write signal xcfx86I which can write into only the light-emitting element L2 is in a range of about 1-2 volts. When the light-emitting element L2 is turned on, that is, in the light-emitting state, the amount of light thereof is determined by the amount of current of the write signal xcfx86I. Accordingly, the light-emitting elements may emit the light at any desired amount of light. In order to transfer on-state to the next element, it is necessary to first turn off the element in on-state by temporarily dropping the voltage of the write signal xcfx86I down to zero volts.
The self-scanning light-emitting device described above may be fabricated by arraying a plurality of chips each thereof being 600 dpi (dot per inch)/128 light-emitting points and having 5.4 mm length. These chips are fabricated on a wafer and obtained by dicing them.
An example of an element arrangement in a chip for the self-scanning light-emitting device is schematically shown in FIG. 2. In the figure, L1-L128 designate light-emitting elements, T1-T128 transfer elements, 40 and 50 bonding pads for clock pulses xcfx861 and xcfx862, 60 a bonding pad for a start pulse xcfx86s, 70 a bonding pad for a write signal xcfx86I, 80 a bonding pad for a power supply VGK, and 90 a bonding pad for an output Dout, respectively. Reference numeral 100 denotes the outer line of the chip.
In the element arrangement shown in FIG. 2, a number of metal wirings are required for connecting the light-emitting elements and transfer element in an array fashion. In particular, four metal wirings for xcfx861, xcfx862, VGK, and diode connection make a detour around the bonding pads 40, 50 and 70 provided at a center of the chip.
FIG. 3 shows the metal wirings around the bonding pad 40 for xcfx861. In the figure, an example is shown wherein a current limiting resistor R1 (see FIG. 1) is built in the chip. Reference numerals 2, 3, 4 and 5 designate xcfx861 wiring, xcfx862 wiring, VGK wiring, and diode connection wiring, respectively. Apparent from the figure, these wirings are formed so as to make a detour around the bonding pad 40.
Such detour of wiring causes the problem in that the size of a chip is enlarged. In order to resolve this problem, there is an approach such that the wirings are formed in a two-layer structure as shown in FIG. 4. That is, the VGK wiring 4 and diode connection wiring 5 are formed under the xcfx861 wiring 2 and xcfx862 wiring 3. In FIG. 4, the portion where the wiring 4 and 5 are crossed with the wirings 2 and 3 is shown as a cross under wiring portion 6 circled by a dotted line 6. Also, at the portion where the xcfx861 wiring 2 and xcfx862 wiring are crossed each other, the xcfx862 wiring 3 is formed under the xcfx861 wiring 2. In FIG. 4, the portion where the xcfx861 wiring 2 and xcfx862 wiring 3 are crossed each other is denoted as a cross under wiring portion 8 circled by a dotted line.
Referring to FIG. 5, there is shown a cross sectional view of the cross under portion 8 in FIG. 4. A pnpn-structure constituting a three-terminal light-emitting thyristor is constructed by stacking a p-type semiconductor layer 30, an n-type semiconductor layer 32, a p-type semiconductor layer 34, and an n-type semiconductor layer 36 in this order on a p-type semiconductor substrate 10. It should be noted that the pnpn structure may be used in which an n-type semiconductor layer, a p-type semiconductor layer, an n-type semiconductor layer, and a p-type semiconductor layer are stacked in this order on an n-type semiconductor substrate.
A lower metal wiring 18 is provided on the portion of the pnpn-structure isolated in an island by a groove 22. The lower metal wiring 18 is electrically isolated from the substrate 10 by the pnpn-structure.
The lower metal wiring 18 is connected to an upper metal wiring 16 through contact holes 20 opened in a insulating film 14 deposited on the above described structure, resulting in a cross under wiring. The upper wiring 16 and lower wiring 18 constitute together one wiring, i.e. the xcfx862 wiring 3 (see FIG. 4). One wiring 25 crossing to the xcfx862 wiring 3 in FIG. 5 corresponds to the xcfx861 wiring 2 in FIG. 4. In this manner, the lower wiring 18 is electrically insulated from the upper wiring 25 by the insulating film 14, so that the crossing of both wirings is possible.
As the self-scanning light-emitting device is based on a thyristor of pnpn-structure, if a voltage is applied to the pnpn-structure isolated in an island by a groove from the metal wiring provided on the pnpn-structure, xe2x80x9clatch-up phenomenonxe2x80x9d may be caused. When xe2x80x9clatch-up phenomenonxe2x80x9d is caused at the pnpn-structure, the thyristor may not only operate normally, but also has a risk in that a large current flows through the thyristor resulting in breakdown.
An object of the present invention is to provide a cross under metal wiring structure which may prevent xe2x80x9clatch-upxe2x80x9d from causing at a pnpn-structure.
The present invention is a cross under metal wiring structure for a self-scanning light-emitting device including a self-scanning transfer element array having such a structure that a plurality of three-terminal transfer elements of pnpn-structure each having a control electrode are arranged, the control electrodes of the transfer elements neighbored to each other are connected via first electrical means, a power supply line is connected to the control electrodes via second electrical means, and clock lines are connected to one of two terminals except the control electrode of each of the transfer elements; and a light-emitting element array having such a structure that a plurality of three-terminal light-emitting elements of pnpn-structure are arranged, the control electrodes of the light-emitting element array are connected to the control electrodes of the transfer element array, and a line for applying a write signal connected to one of two terminals except the control electrode of each of the light-emitting elements is provided. The cross under metal wiring structure is provided on the pnpn-structure isolated in an island by a groove.
According to the present invention, the following approaches can be taken to prevent xe2x80x9clatch-upxe2x80x9d due to the applied voltage from causing at a light-emitting thyristor of pnpn-structure isolated in an island by a groove when a cross under metal wiring is formed on the isolated pnpn-structure.
(1) It is intended that a potential difference is not caused between the upper two layers of the pnpn-structure.
(2) The material of a lower wiring is selected so that the lower wiring is made ohmic contact with the topmost layer of the pnpn-structure.
(3) An insulating-type semiconductor layer is provided between the topmost layer of the pnpn-structure and the lower wiring formed on the topmost layer.
(4) The topmost layer of the pnpn-structure is removed to form a pnp-structure or npn-structure on which a lower wiring is formed.
According to a first aspect of the present invention, the cross under metal wiring structure comprises a lower wiring provided on a topmost layer of the pnpn-structure isolated in an island by a groove, and an upper wiring connected to the lower wiring through a first contact hole opened in an insulating film covered the isolated pnpn-structure and to a layer just below the topmost layer through a second contact hole opened in the insulating film.
According to a second aspect of the present invention, the cross under metal wiring structure comprises a lower wiring provided on a topmost layer of the, pnpn-structure isolated in an island by a groove, and an upper wiring connected to the lower wiring through a contact hole opened in an insulating film covered the isolated pnpn-structure, wherein the lower wiring is made of material which makes non-ohmic contact with the topmost layer.
According to a third aspect of the present invention, the cross under metal wiring structure comprises an insulating layer provided on a topmost layer of the pnpn-structure isolated in an island by a groove, a lower wiring provided on the insulating layer, and an upper wiring connected to the lower wiring through a contact hole opened in an insulating film covered the isolated pnpn-structure.
According to a fourth aspect of the present invention, the pnpn-structure is changed into a pnp-structure or npn-structure by removing a topmost layer of the pnpn-structure. The cross under metal wiring structure comprises a lower wiring provided on a topmost layer of the pnp-structure or npn-structure isolated in an island by a groove, and an upper wiring connected to the lower wiring through a contact hole opened in an insulating film covered the isolated pnp-structure or npn-structure.